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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.10.1 Auto Refresh Command
CK
CK
CKE
(High)
CS
RAS
CAS
WE
A0-An
BA0,BA1
= Don't Care
7.11 Self Referesh
The SELF REFRESH command can be used to retain data in the LPDDR SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without external clocking. The
LPDDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command
is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are “Don?t Care”
during Self Refresh. The user may halt the external clock one clock after the SELF REFRESH command is
registered.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The clock is
internally disabled during Self Refresh operation to save power. The minimum time that the device must remain in
Self Refresh mode is t RFC .
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to
CKE going back High. Once Self Refresh Exit is registered, a delay of at least t XS must be satisfied before a valid
command can be issued to the device to allow for completion of any internal refresh in progress.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when
CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is
recommended.
In the Self Refresh mode, one additional power-saving option exist: Partial Array Self Refresh (PASR); It is described
in the Extended Mode Register section.
Publication Release Date : Oct, 15, 2012
- 41 -
Revision : A01-004
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功能描述:IC LPDDR SDRAM 256MBIT 60VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6